By T.J.HOGAN I.R.THOMAS
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Extra info for AISC - Design of Structural Connections 4th 1994
Short-circuit power leakage power The cause of each component and the significance of its contribution to the total power consumption will be explained as follows. 1 DYNAMIC POWER Dynamic power occurs when the output of the CMOS logic gate switches. During the switch, the output parasitic capacitances are either charged up to the supply voltage level or discharged to the ground level (See Fig. 1). During the charge-up phase, half of the energy supplied by the power source is stored in the output loading capacitance.
It is the most accurate way of predicting path timing. Static timing analysis is conceptually very different from the dynamic analysis in that no input patterns are required. The false-path problem associated with the static timing analysis is examined and different solutions are provided. Two distinct approaches in static timing analysis, path-oriented approach and block-oriented approach, are presented. Because the block-oriented approach is extremely efficient and widely used in high-performance VLSI design, it will be the focus of our discussion.
The second technique was called the relaxation method. This method divided the original problem into electrical and thermal systems. They were solved separately and the solutions were obtained by applying successive relaxation between the two systems. Both techniques have their own advantages and disadvantages. The direct method is more general and powerful for analyzing different problems such as dc, transient, and dc transfer characteristics. However, it is computationally more expensive and may not be able to handle all nonlinearities of the system.