Download Advanced ASIC Chip Synthesis Using Synopsys Tools by Himanshu Bhatnagar PDF

By Himanshu Bhatnagar

Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complicated options and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the whole ASIC layout movement method distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time program of Synopsys instruments, used to wrestle a number of difficulties noticeable at VDSM geometries. Readers could be uncovered to a good layout method for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties similar to every part of the layout movement are pointed out, with recommendations and work-around defined intimately. moreover, an important concerns comparable to format, along with clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the booklet comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, exact in the direction of optimum synthesis answer.
objective audiences for this publication are training ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT recommendations.

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This operation is ASIC DESIGN METHODOLOGY 11 usually performed a number of times until the timing requirements are satisfied. 6 Placement, Routing and Verification As the name suggests, the layout tool performs the placement and routing. There are a number of methods in which this step could be performed. However, only issues related to synthesis are discussed in this section. The quality of floorplan and placement is more critical than the actual routing. Optimal cell placement location, not only speeds up the final routing, but also produces superior results in terms of timing and reduced congestion.

Also, the clock tree has been inserted in the design by the layout tool. The clock tree insertion modifies the existing structure of the design. In other words, the netlist in the layout tool is different from the original netlist present in DC. This is because of the fact that the design present in the layout tool contains the clock tree, 32 Chapter 2 whereas the original design in DC does not contain this information. Therefore, the clock tree information should somehow be transferred to the design residing in DC or PT.

In comparison, the formal method would take a few hours to perform a similar verification. The last part involves verifying the gate-level netlist against the gate-level netlist. This too is a significant step for the verification process, since it is mainly used to verify – what has gone into the layout versus what has come out of the layout. What comes out of the layout is obviously the clock tree inserted netlist (flat or hierarchical). This means that the original netlist that 10 Chapter 1 goes into the layout tool is modified.

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